q3-dsb-labs/ch4/timebase_tb.sv

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`timescale 1ns/1ps
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module timebase_tb #(parameter N = 21);
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logic clk;
logic reset;
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logic [N-1:0] count;
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timebase test (clk, reset, count);
always
#5 clk = ~clk;
initial
clk = 0;
initial begin
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$dumpfile("output.vcd");
$dumpvars;
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reset = 1;
#10; reset = 0;
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#200; reset = 1;
$finish;
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end
endmodule