2025-02-10 14:29:25 +01:00
|
|
|
`timescale 1ns/1ps
|
|
|
|
|
2025-02-11 13:13:58 +01:00
|
|
|
module timebase_tb #(parameter N = 21);
|
2025-02-10 14:29:25 +01:00
|
|
|
|
|
|
|
logic clk;
|
|
|
|
logic reset;
|
2025-02-11 13:13:58 +01:00
|
|
|
logic [N-1:0] count;
|
2025-02-10 14:29:25 +01:00
|
|
|
|
|
|
|
timebase test (clk, reset, count);
|
|
|
|
|
|
|
|
always
|
|
|
|
#5 clk = ~clk;
|
|
|
|
initial
|
|
|
|
clk = 0;
|
|
|
|
|
|
|
|
initial begin
|
2025-02-10 15:16:23 +01:00
|
|
|
$dumpfile("output.vcd");
|
|
|
|
$dumpvars;
|
2025-02-10 15:34:20 +01:00
|
|
|
reset = 1;
|
|
|
|
#10; reset = 0;
|
2025-02-10 15:16:23 +01:00
|
|
|
#200; reset = 1;
|
|
|
|
$finish;
|
2025-02-10 14:29:25 +01:00
|
|
|
end
|
|
|
|
|
|
|
|
endmodule
|