33 lines
620 B
Systemverilog
33 lines
620 B
Systemverilog
`timescale 1ns/1ps
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module motorcontrol_tb();
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logic clk;
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logic rst;
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logic direction;
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logic [20:0] count;
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logic pwm;
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timebase test1 (clk, rst, count);
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motorcontrol test2 (clk, rst, direction, count, pwm);
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always
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#5 clk = ~clk; // period 10ns (100 MHz)
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initial
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clk = 0;
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initial begin
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$dumpfile("output.vcd");
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$dumpvars;
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rst = 1; direction = 0;
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#10; rst = 0;
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#19999990; rst = 1; direction = 1;
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#10; rst = 0;
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#19999990; rst = 1;
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#10; rst = 0;
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$finish;
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end
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endmodule
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