49 lines
864 B
Systemverilog
49 lines
864 B
Systemverilog
`timescale 1ns/1ps
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module motorcontrol #(parameter N=21)
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(input logic clk,
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input logic rst,
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input logic direction,
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input logic [N-1:0] count_in,
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output logic pwm);
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typedef enum logic[1:0] {reset, high, low} pwm_state;
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pwm_state state, next_state;
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always_ff @(posedge clk)
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if (rst)
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state <= reset;
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else
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state <= next_state;
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always_comb begin
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case (state)
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reset:
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begin
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pwm = 0;
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next_state = high;
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end
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high:
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begin
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pwm = 1;
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if (direction == 0 && count_in >= 21'd100_000)
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next_state = low;
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else if ( direction == 1 && count_in >= 21'd200_000)
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next_state = low;
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else
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next_state = state;
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end
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low:
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begin
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pwm = 0;
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next_state = state;
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end
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default:
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begin
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pwm = 0;
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next_state = reset;
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end
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endcase
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end
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endmodule
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