27 lines
459 B
Systemverilog
27 lines
459 B
Systemverilog
`timescale 1ns/1ps
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module inputbuffer
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(input logic clk,
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input logic sensor_l_in,
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input logic sensor_m_in,
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input logic sensor_r_in,
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output logic sensor_l_out,
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output logic sensor_m_out,
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output logic sensor_r_out);
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logic [2:0]Q_a;
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always_ff @(posedge clk)
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begin
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Q_a[2] <= sensor_l_in;
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Q_a[1] <= sensor_m_in;
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Q_a[0] <= sensor_r_in;
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sensor_l_out <= Q_a[2];
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sensor_m_out <= Q_a[1];
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sensor_r_out <= Q_a[0];
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end
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endmodule
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