12 lines
242 B
Systemverilog
12 lines
242 B
Systemverilog
`timescale 1ns/1ps
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module timebase #(parameter N = 18)
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(input logic clk,
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input logic reset,
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output logic [N-1:0] count);
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always_ff @(posedge clk, posedge reset)
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if(reset) count <= 0;
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else count <= count + 1;
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endmodule
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