111 lines
2.1 KiB
Systemverilog
111 lines
2.1 KiB
Systemverilog
`timescale 1ns/1ps
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module controller #(parameter N=21)
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(input logic clk,
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input logic reset,
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input logic sensor_l,
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input logic sensor_m,
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input logic sensor_r,
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input logic [N-1:0] count_in,
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output logic count_reset,
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output logic motor_l_reset,
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output logic motor_l_direction,
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output logic motor_r_reset,
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output logic motor_r_direction);
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typedef enum logic [2:0] {Central, Forward, Gentle_l, Sharp_l, Gentle_r, Sharp_r} control_state;
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control_state state, next_state;
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always_ff @(posedge clk, posedge count_reset, posedge reset) begin
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if(count_reset | reset)
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state <= Central;
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else
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state <= next_state;
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end
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logic [2:0] sensors_lmr;
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assign sensors_lmr = {sensor_l, sensor_m, sensor_r};
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always_comb begin
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if (count_in >= 21'd2_000_000 | reset)
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count_reset = 1;
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else
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count_reset = 0;
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case(state)
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Central: begin
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motor_l_reset = 1;
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motor_l_direction = 0;
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motor_r_reset = 1;
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motor_r_direction = 0;
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case(sensors_lmr)
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3'b000, 3'b010, 3'b101, 3'b111: next_state = Forward;
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3'b001: next_state = Gentle_l;
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3'b011: next_state = Sharp_l;
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3'b100: next_state = Gentle_r;
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3'b110: next_state = Sharp_r;
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default: next_state = Central;
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endcase
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end
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Forward: begin
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motor_l_reset = 0;
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motor_l_direction = 1;
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motor_r_reset = 0;
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motor_r_direction = 0;
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next_state = state;
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end
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Gentle_l: begin
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motor_l_reset = 1;
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motor_l_direction = 0;
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motor_r_reset = 0;
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motor_r_direction = 0;
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next_state = state;
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end
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Sharp_l: begin
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motor_l_reset = 0;
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motor_l_direction = 0;
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motor_r_reset = 0;
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motor_r_direction = 0;
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next_state = state;
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end
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Gentle_r: begin
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motor_l_reset = 0;
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motor_l_direction = 1;
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motor_r_reset = 1;
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motor_r_direction = 0;
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next_state = state;
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end
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Sharp_r: begin
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motor_l_reset = 0;
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motor_l_direction = 1;
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motor_r_reset = 0;
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motor_r_direction = 1;
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next_state = state;
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end
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default: begin
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motor_l_reset = 1;
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motor_l_direction = 0;
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motor_r_reset = 1;
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motor_r_direction = 0;
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next_state = state;
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end
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endcase
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end
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endmodule
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