Added counter

ch4/timebase.sv

@@ -1,8 +1,11 @@
-module timebase 
+`timescale 1ns/1ps
+
+module timebase #(parameter N = 18) 
    (input logic clk,
     input logic reset,
-    output logic [?:0] count);
-
-
+    output logic [N-1:0] count);
 
+  always_ff @(posedge clk, posedge reset)
+    if(reset) count <= 0;
+    else count <= count + 1;
 endmodule

ch4/timebase.sv.bak

@@ -1,5 +0,0 @@
-`timescale 1ns/1ps
-
-Aanpassing van lasse
-
-Aanpassing van Timo

ch4/timebase_tb.sv

@@ -4,7 +4,7 @@ module timebase_tb();
 
    logic clk;
    logic reset;
-   logic [20:0] count;
+   logic [17:0] count;
    
    timebase test (clk, reset, count);
 
@@ -14,8 +14,12 @@ module timebase_tb();
       clk = 0;
 
    initial begin
-          reset = 1; 
-     #10; reset = 0; 
+      $dumpfile("output.vcd");
+      $dumpvars;
+   
+          reset = 0; 
+     #200; reset = 1; 
+      $finish;
    end
 
 endmodule