13 lines
236 B
Systemverilog
13 lines
236 B
Systemverilog
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module inputbuffer
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(input logic clk,
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input logic sensor_l_in,
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input logic sensor_m_in,
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input logic sensor_r_in,
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output logic sensor_l_out,
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output logic sensor_m_out,
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output logic sensor_r_out);
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endmodule
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