22 lines
276 B
Systemverilog
22 lines
276 B
Systemverilog
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`timescale 1ns/1ps
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module timebase_tb();
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logic clk;
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logic reset;
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logic [20:0] count;
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timebase test (clk, reset, count);
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always
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#5 clk = ~clk;
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initial
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clk = 0;
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initial begin
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reset = 1;
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#10; reset = 0;
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end
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endmodule
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