q3-dsb-labs/ch4/timebase.sv

`timescale 1ns/1ps

module timebase #(parameter N = 21) 
   (input logic clk,
    input logic reset,
    output logic [N-1:0] count);

  always_ff @(posedge clk, posedge reset)
    if(reset) count <= 0;
    else count <= count + 1;
endmodule