`timescale 1ns/1ps

module timebase_tb();

   logic clk;
   logic reset;
   logic [17:0] count;
   
   timebase test (clk, reset, count);

   always
      #5 clk = ~clk;
   initial
      clk = 0;

   initial begin
      $dumpfile("output.vcd");
      $dumpvars;
   
          reset = 0; 
     #200; reset = 1; 
      $finish;
   end

endmodule