`timescale 1ns/1ps

module motorcontrol_tb();

   logic clk;
   logic rst;
   logic direction;
   logic [20:0] count;
   logic pwm;

   timebase test1 (clk, rst, count);

   motorcontrol test2 (clk, rst, direction, count, pwm);

   always
      #5 clk = ~clk;  // period 10ns (100 MHz)
   initial
      clk = 0;

   initial begin
      $dumpfile("output.vcd");
      $dumpvars;
      rst = 1; direction = 0;   
      #10;       rst = 0; 
      #19999990; rst = 1; direction = 1;
      #10;       rst = 0;
      #19999990; rst = 1;                              
      #10;       rst = 0;
      $finish;
   end

endmodule