`timescale 1ns/1ps

module inputbuffer
   (input logic clk,
    input logic sensor_l_in,
    input logic sensor_m_in, 
    input logic sensor_r_in,
    output logic sensor_l_out,
    output logic sensor_m_out, 
    output logic sensor_r_out);


logic [2:0]Q_a; 


always_ff @(posedge clk)
	begin
	Q_a[2] <= sensor_l_in;
	Q_a[1] <= sensor_m_in;
	Q_a[0] <= sensor_r_in;
	sensor_l_out <= Q_a[2];
	sensor_m_out <= Q_a[1];
	sensor_r_out <= Q_a[0];
	end

endmodule